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low skew, 1-to-4, crystal oscillator/lvcmos-to- 3.3v lvpecl fanout buffer ics8535i-31 idt? / ics? 3.3v lvpecl fanout buffer 1 ICS8535AGI-31 rev. a august 16, 2007 general description the ics8535i-31 is a low skew, high performance 1-to-4 3.3v crystal oscillator/lvcmos-to-3.3v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the ic s8535i-31 has selectable single ended clock or crystal inputs. the single ended clock input accepts lvcmos or lvttl input leve ls and translate them to 3.3v lvpecl levels. the output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics8535i-31 ideal for those applications demanding well defined performance and repeatability. features ? four differential 3.3v lvpecl outputs ? selectable lvcmos/lvttl clk or crystal inputs ? clk can accept the following input levels: lvcmos, lvttl ? maximum output frequency: 266mhz ? output skew: 30ps (typical) ? part-to-part skew: 200ps (maximum) ? propagation delay: 1.75ns (maximum) ? additive phase jitter, rms: 0.057ps (typical) ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? replaces the ics8535i-11 ? available in both standard (rohs 5) and lead-free (rohs 6) packages block diagram hiperclocks? ic s q0 nq0 q1 nq1 clk_en clk_sel clk d le q 0 1 q2 nq2 q3 nq3 osc xtal_in xtal_out pullup pulldown pulldown 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc nc xtal_out xtal_in nc clk clk_sel clk_en v ee v cc q0 nq0 v cc q1 nq1 q2 nq2 v cc q3 nq3 ics8535i-31 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view pin assignment
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 2 ICS8535AGI-31 rev. a august 16, 2007 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v ee power negative supply pin. 2 clk_en input pullup synchronizing clock enable. when high, clock outputs follows clock input. when low, q outputs are forced low, nq outputs are forced high. lvcmos / lvttl interface levels. 3 clk_sel input pulldown clock select input. when high, selects xtal inputs when low, selects clk input. lv cmos / lvttl interface levels. 4 clk input pulldown single-ended clock input. lvcmos/lvttl interface levels. 5, 8, 9 nc unused no connect. 6, 7 xtal_in, xtal_out input crystal oscillator interface. xtal_i n is the input. xtal_out is the output. 10, 13, 18 v cc power positive supply pins. 11, 12 nq3, q3 output diff erential output pair. l vpecl interface levels. 14, 15 nq2, q2 output diff erential output pair. l vpecl interface levels. 16, 17 nq1, q1 output diff erential output pair. l vpecl interface levels. 19, 20 nq0, q0 output diff erential output pair. l vpecl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 3 ICS8535AGI-31 rev. a august 16, 2007 function tables table 3a. control input function table after clk_en switches, the clock outputs are disabled or enab led following a rising and falling input clock or crystal oscillat or edge as shown in figure 1. in the active mode, the state of the outputs are a function of the clk input as described in table 3b. figure 1. clk_en timing diagram table 3b. clock input function table inputs outputs clk_en clk_sel selected source q0:q3 nq0:nq3 0 0 clk0 disabled; low disabled; high 0 1 clk1 disabled; low disabled; high 1 0 clk0 enabled enabled 1 1 clk1 enabled enabled inputs outputs clk q0:q3 nq0:nq3 0lowhigh 1highlow clk clk_en nq0:nq3 q0:q3 enabled disabled
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 4 ICS8535AGI-31 rev. a august 16, 2007 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuos current surge current 50ma 100ma package thermal impedance, ja 73,2 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v i ee power supply current 65 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk, clk_sel v cc = v in = 3.465v 150 a clk_en v cc = v in = 3.465v 5 a i il input low current clk, clk_sel v cc = 3.465v, v in = 0v -5 a clk_en v cc = 3.465v, v in = 0v -150 a
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 5 ICS8535AGI-31 rev. a august 16, 2007 table 4c. lvpecl dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v table 5. crystal characteristics ac electrical characteristics table 6. ac characteristics, v cc = 3.3v 5%, t a = 0c to 70c all parameters measured at ? 266mhz unless noted otherwise. note 1: measured from v cc /2 of the input to the differential output crossing point. note 2: defined as skew between outputs at the sa me supply voltage and with equal load conditions. measured at the differential output crossing point. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the output s are measured at the differential cross points. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 12 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf drive level 1mw parameter symbol test conditio ns minimum typical maximum units f max output frequency 266 mhz t pd propagation delay; note 1 1.4 1.75 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.057 ps t sk(o) output skew; note 2, 3 30 ps t sk(pp) part-to-part skew; note 3, 4 200 ps t r / t f output rise/fall time 20% to 80% 300 600 ps odc output duty cycle 46 54 %
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 6 ICS8535AGI-31 rev. a august 16, 2007 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.057ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m offset frequency (hz) ssb phase noise dbc/hz
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 7 ICS8535AGI-31 rev. a august 16, 2007 parameter measureme nt information 3.3v core/3.3v output load ac test circuit output skew output rise/fall time propagation delay output duty cycle/pulse width/period , , scope qx nqx lvpecl v ee v cc 2v 1.3v 0.165v nqx qx nqy qy t sk(o) clock outputs 20% 80% 80% 20% t r t f v swing , t pd v cc 2 nq0:nq3 q0:q3 clk t pw t period t pw t period odc = x 100% nq0:nq3 q0:q3
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 8 ICS8535AGI-31 rev. a august 16, 2007 application information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1kw resistor can be tied from xtal_in to ground. clk input for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. crystal input interface the ics8535i-31 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. these same capacitor values will tune any 18pf parallel resonant crystal over the frequency range and other parameters specified in this data sheet. the optimum c1 and c2 values can be slightly adjusted for different board layouts . figure 2. crystal input interface xtal_in xtal_out x1 18pf parallel crystal c1 c2
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 9 ICS8535AGI-31 rev. a august 16, 2007 lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 3. general diagram for lvcmos driver to xtal input interface termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impe dance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to groun d) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination fi gure 4b. 3.3v lvpecl output termination xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v cc v cc v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 10 ICS8535AGI-31 rev. a august 16, 2007 power considerations this section provides information on power dissipati on and junction temperature for the ics8535i-31. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8535i-31 is the sum of th e core power plus the power plus the power dissipated in the lo ad(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 65ma = 225.2mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power _max (3.465v, with all outputs switching) = 225.2mw + 120mw = 345.2mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the ap propriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per meter and a multi-layer boar d, the appropriate value is 66.6c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.345w * 66.6c/w = 108c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 7. thermal resistance ja for 20 lead tssop, forced convection ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 11 ICS8535AGI-31 rev. a august 16, 2007 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. figure 5. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v - (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v - 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 12 ICS8535AGI-31 rev. a august 16, 2007 reliability information table 8. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics8535i-31 is: 428 package outline and package dimensions package outline - g suffix for 20 lead tssop t able 9. package dimensions 20 lead tssop reference document: jedec publication 95, mo-153 ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 13 ICS8535AGI-31 rev. a august 16, 2007 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature ICS8535AGI-31 ics8535agi31 20 lead tssop tube -40 c to 85 c ICS8535AGI-31t ics8535agi31 20 lead tssop 2500 tape & reel -40 c to 85 c ICS8535AGI-31lf ics8535ai31l ?lead-free? 20 lead tssop tube -40 c to 85 c ICS8535AGI-31lft ics8535ai31l ?lead-free? 20 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applicat ions, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics8535i-31 low skew, 1-to-4, crystal oscillator /lvcmos-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 14 ICS8535AGI-31 rev. a august 16, 2007 revision history sheet rev table page description of change date a t10 8 9 13 added recommendations for unused input and output pins. added lvcmos-to-crystal interface section. ordering information table - added lead-free marking. 8/16/07
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